This invention pertains to semiconductor devices, and more particularly to trenched semiconductor devices having relatively high breakdown voltages.
Trenched double diffused metal oxide silicon (DMOS) transistors such as the ones discussed in the article, "An Ultra-Low ON Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process" by Ueda, Takagi & Kano (IEEE Transactions on Electron Devices, Vol. ED-34, No. 4, April 1987, pp. 926-930) offer a method of significantly reducing the onresistance per unit area compared with conventional vertical DMOS devices.
Prior art DMOS transistors are described, for example, in "Self-Aligned UMOSFET's with a Specific On-Resistance of 1 m.OMEGA..multidot.cm.sup.2 ", Chang et al., IEEE Transactions on Electron Devices, Vol. ED-34, No. 11, November 1987, pp. 2329-2334, and "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process", Ueda et al., IEEE Transactions on Electron Devices, Vol. ED-34, No. 4, pp. 926-930, April 1987.
One example is the low voltage prior art trenched DMOS transistor shown in the cross-sectional view of FIG. 1. As shown in FIG. 1, trenched DMOS transistor 10 includes substrate 11, upon which is formed an epitaxial layer 12, which is more lightly doped than substrate 11. Metallic layer 13 is formed on the bottom of substrate 11, allowing an electrical contact 14 to be made to substrate 11. As is known to those of ordinary skill in the art, DMOS transistors also include source regions 16a, 16b, 16c, and 16d, and body regions 15a and 15b. Epitaxial region 12 serves as the drain. In the example shown in FIG. 1, substrate 11 is relatively highly doped with N type dopants, epitaxial layer 12 is relatively lightly doped with N type dopants, source regions 16a, 16b, 16c, and 16d are relatively highly doped with N type dopants, and body regions 15a and 15b are relatively highly doped with P type dopants. A polycrystalline silicon gate electrode 18 is formed within a trench, and is electrically insulated from other regions by gate dielectric layer 17 formed on the bottom and sides of the trench containing gate electrode 18.
FIG. 2 shows another trenched DMOS transistor 20 designed for higher voltage operation. In DMOS transistor 20, trench 18 extends only part way through epitaxial region 12. By extending the trench only part way through lightly doped epitaxial region 12, higher voltage operation is obtained.
However, the development of higher voltage devices is not without its problems. Two problems in particular are the potential reduction in breakdown voltage caused by the corner regions at the bottom of the trench because of the increase of the electric field at corners, and the resistance caused because carriers do not spread out once they leave the channel region. In the fabrication of low voltage devices (30-90 V), it is possible to choose a trench depth so its bottom surface is below the interface of the epitaxial layer 12 and the substrate 11 as shown in FIG. 1. The heavy doping concentration in substrate 11 at the corners of the trench limits carrier velocity, increasing the breakdown voltage of the device. In addition, with the carriers flowing from channel 24a, 24b (FIG. 1) directly along an accumulated surface (along the sidewall of the trench) and directly into heavily doped substrate 11, there is little additional resistance added by lightly doped epitaxial layer 12. The breakdown voltage of the trenched DMOS structure of FIG. 1 may be limited by one or more of the following phenomena:
1. Avalanche breakdown at the P+/N junction formed at the interface between P+ body region 15a, 15b and N type epitaxial region 12.
2. Field plate induced breakdown along the sides or bottom of the trench caused by the electric field.
3. Reachthrough breakdown caused by the spreading of the depletion region from the P+/N junction formed at the interfere between P+ body regions 15a, 15b and epitaxial region 12 through epitaxial region 12 to N+ substrate 11.
The above phenomena related to breakdown voltages are well known and are described, for example, in "Breakdown Voltage of Planar Silicon Junctions", Leistiko and Grove, Solid State Electronics, Pergeman Press 1966, Vol. 9, pp. 847-852, and "Optimization of Discrete High Power MOS Transistors", Blanchard, Dissertation Submitted to the Department of Electrical Engineering of Stanford University, December 1981.
The fabrication of trenched DMOS devices with higher breakdown voltages (100 V or greater) may not be possible when the trench extends into N+ substrate 11. However, if the trench ends in N- type epitaxial layer 12 as shown in FIG. 2, the problem of cornerenhanced breakdown and increased on-resistance mentioned above may occur.
Accordingly, prior art techniques for fabrication of trench DMOS devices have not lead to the fabrication of trench DMOS devices with high breakdown voltages and low on-resistances per unit area.